The present invention relates to a data transferring system in a data processing system in which a bus controller, a memory unit and a plurality of data processing units are connected in parallel on a common bus having data lines and a control signal line, and data is transferred between the data processing units and the memory unit or between data processing units under the control of the bus controller. More particularly, the invention relates to a system of detecting and processing data transfer abnormalities such as parity errors.
FIG. 1A is a block diagram of a prior art data processing system of this general type.
In FIG. 1A, reference numeral 1 designates a bus controller which controls the right of use of a bus B, supplies a clock signal and conducts a transfer abnormality detecting operation such as a parity check. Reference numeral 2 designates a memory unit connected to the bus B, and reference numerals 3.sub.1, 3.sub.2, . . . 3.sub.i . . . 3.sub.n designate data processing units. The common bus B is constituted by data lines for transmitting data between these units and control signal lines for transmitting various signals other than data.
FIG. 2A is a connection diagram showing the elements of FIG. 1A in more detail. Only one data processing unit is shown in FIG. 2A; however, it should be noted that, similar to FIG. 1A, a plurality of data processing units are provided. The common bus control of the bus controller is not related directly to the invention, and therefore its specific arrangement will not be described.
In FIG. 2A, reference numeral 1 designates the bus controller, 11 a transfer abnormality check circuit, 12 a data signal receiver, 13 a transfer abnormality signal transmission driver, 2 the memory unit, 21 a memory element, 22 a drive signal receiver, 23 an address receiver, 3 the data processing unit, 31 a transfer control circuit, 32 an address register, 33 a data register, 34 a transfer abnormality setting flip-flop, 35, 38 and 39 receivers, and 36 and 37 drivers.
FIG. 1B is a timing chart showing the operation of the data processing unit wherein the data processing unit reads data out of the memory unit. In FIG. 1B, reference character CLK designates a synchronizing clock pulse for data transfer, the clock pulse being supplied from the bus controller 1 to the data processing unit 3 or to the memory unit 2 as the case may be. BRQ designates a signal provided when the data processing unit 3 makes a request for the use of the bus to the bus controller 1, GRT a bus use permission signal which is applied to the data processing unit 3 from the bus controller 1, MOVE a data transfer operation indication signal which is applied from the data processing unit 3 to the bus controller 1 and the memory 2, DRCT a transfer direction indication signal which is outputted by the signal MOVE (the dotted line designating that the transfer direction is from the memory unit to the data processing unit), and ADDRESS an address signal for the memory unit 2 which is outputted by the data processing unit 3 with the same timing as the signal MOVE. These signals are supplied through the control signal lines of the common bus.
Further in FIG. 1B, reference character DATA designates a data signal read out of the memory unit 2, TES a transfer abnormality signal which is subjected to decision by the bus controller 1 according to the data signal read out of the memory unit 2, REG a signal of the data register 33 (shown in FIG. 2A only) which is generated in the data processing unit and used for storing data read out of the memory unit 2, and FF a signal from the flip-flop 34 for storing data transfer abnormalities.
FIG. 2B is a timing chart showing in more detail the conditions of various signals during the period of time T.sub.2 in FIG. 1B. In FIG. 2B and FIG. 1B, like signals are designated by like reference characters or numerals.
In FIG. 2B, lines extending in the direction of the horizontal axis are marked off into several lengths with reference numerals or characters. These lengths represent the delay times of signals, such as MOVE and TES, indicated on the left-hand side in elements designated by reference numerals or characters such as 36, B and 22. The delay of the memory element in the memory unit 2 is about 60 ns from the clock signal CLK and the delays of the other component circuits are determined according to those of Schottky TTL elements. The bus B is typically a mother board wiring plate about 50 cm long.
FIG. 2C shows the arrangement of the transfer abnormality check circuit 11 in more detail. In FIG. 2C, reference numerals 111 and 113 designate a data parity check circuit for the higher byte and a data parity check circuit for the lower byte, respectively, of a data word, and 113 designates an OR gate. Data delivered from the receiver 12 is subjected to odd-number parity checking by the data parity check circuits 111 and 112. If any parity error is found, a signal indicating this fact is applied through the OR gate 113 to the transfer abnormality signal transmission drive 13.
FIG. 2D shows the arrangement of the transfer control circuit 31 in more detail. In FIG. 2D, reference numeral 311 designates an inverter, 312 and 313 flip-flops, and 314 and 315 AND gates. The operation of the circuit shown in FIGS. 1A and 2A will be described with reference to FIGS. 1B, 2B, 2C and 2D.
It is assumed that the data processing unit 3.sub.i has delivered a bus B request signal BRQ.sub.i to the bus controller 1 with the timing T.sub.1 in response to a transfer request signal A. The use request signal is stored in the flip-flop 312.
Among the request signal BRQ.sub.i and the request signals outputted by the other data processing units, the one of highest priority is selected by the bus controller 1. If the request signal BRQ.sub.i is highest in priority, the bus controller 1 applies a bus use permission signal GRT.sub.i to the data processing unit 3.sub.i. As a result, the flip-flop 312 is reset in synchronization with the synchronizing clock signal CLK while the flip-flop 212 is set. In response to the signal GRT.sub.i, the data processing unit 3.sub.i starts a data transfer operation and applies the signal MOVE, the signal DRCT according to the transfer direction signal B, and the address signal ADDRESS to the bus B.
When the data of an address in the memory unit 2 is read out and applied to the bus B, the data is loaded into a register (not shown) in the data processing unit 3.sub.i. At the same time, the data applied to the bus B is checked in the transfer abnormality check circuit 11 of the bus controller 1. The check can be carried out by a variety of checking methods. However, in the embodiment described, a parity check is employed. If the data is found to be abnormal, the transfer abnormality signal TES is applied to the bus B.
In the data processing unit 3.sub.i, the transfer abnormality signal TES is applied to the flip-flop 34 with the timing T.sub.2 whereupon a transfer abnormality processing signal C is outputted so as to be used for the following data processing. The flip-flop 34 is reset by a transfer abnormality reset signal D.
As is apparent from the above description, if it is requested merely to transfer data at the point A (FIG. 2B) where the previous data transfer has been completed, the transfer of the next data can be started. However, if the transfer abnormality processing operation is carried out, then the next data transfer starting time instant is delayed to the point B. Thus, disadvantageously, the data transfer time is increased as a whole. For instance, at the point A in FIG. 2B the data transfer time is 200 ns, but at the point B the data trasfer time is increased by 25% to 250 ns. This causes no serious problem for a memory which has a relatively long access time. However, the above-described time delay will greatly affect a memory such as some types of semiconductor memories and especially an LSI memory whose operating speed is considerably fast, for example, 50 ns.